The present invention relates to semiconductor structures, and more specifically, to a diffusion sidewall to compensate for dopant segregation in silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistors (MOSFETs).
CMOS technologies employ field effect transistors (FETs) that are adjacent or bounded by trenches. The trenches provide isolation (shallow trench isolation or STI) or they may provide a location for other semiconductor devices. Parasitic leakage paths have been found because of the proximity of a semiconductor device to an edge or corner of each trench. Further, semiconductor devices near the active silicon region (RX)/STI interface (e.g., the corner region) shows a lower threshold voltage (Vt), due to the dopant loss because of the dopant segregation at the RX/STI interface, than at the planar portion of the device.